• Nagarajan P,Renuka.M, Manikannan A and Dhanasekaran S, “Design and Simulation of
  a Novel 16T SRAM Cell for Low Power Memory Architecture ”Journal of Circuits, Systems and Computers, ISSN (print): 0218-1266 |ISSN (online):1793-6454, Impact Factor: 1.5, https://doi.org/10.1142/S0218126624500038 , June 2023.(SCI indexed)
• Pandian Nagarajan, Thandabani Kavitha, Nagarajan Ashok Kumar, Alexander Shirly Edward, “POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP. (2023). REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE, ISSN (online): 00354066, Impact Factor: 0.7, https://doi.org/10.59277/RRST-EE.2023.4.19 , December 2023. (SCI indexed)
• Nagarajan P,Renuka.M, Manikannan A and Dhanasekaran S, “Design and Simulation of
  a Novel 16T SRAM Cell for Low Power Memory Architecture ”Journal of Circuits, Systems and Computers, ISSN (print): 0218-1266 |ISSN (online): 1793-6454, Impact Factor: 1.5, https://doi.org/10.1142/S0218126624500038 , June 2023.(SCI indexed)
• Nagarajan P, Ashokkumar N and VenkatRamana P, “Design of implicit pulsed – dual edge triggering flip flop for low power and high speed clocking systems”, International Journal of Wavelets, Multiresolution and Information Processing (IJWMIP), ISSN (print): 0219-6913 , ISSN (online): 1793-690X, Impact Factor:1.276, Vol.17, No.2,June2019,PP.1941009_1-1941009_19 1941009 (19 pages) (SCI indexed)
• C.S. Anita, P. Nagarajan and G. Aditya Sairam, “Fake Job Detection and Analysis Using Machine Learning and Deep Learning Algorithms” , REVISTA GEINTEC-GESTAO INOVACAO E TECNOLOGIAS, ISSN : 2237-0722 , Vol. 11 No. 2 (2021), June 2021, PP. 642-650 ( Web of science – ESCI )
• C.S. Anita, P. Nagarajan , E. Lakshminarayanan and M. Naveen Sankar, “ Machine Vision and Machine Learning based Fruit Quality Monitoring ”, REVISTA GEINTEC-GESTAO INOVACAO E TECNOLOGIAS, ISSN : 2237-0722 , Vol. 11 No. 2 (2021), June 2021, PP. 836-842 ( Web of science – ESCI)
• N Ashokkumar , P Nagarajan, and P Venkat Ramana , “Quad-Rail Sense- Amplifier Based Network-On-Chip Router Design”, Journal of Computational and Theoretical Nanoscience, American scientific publishers, ISSN: 1546- 1955 (Print): EISSN: 1546-1963 (Online), Vol 15, November/December 2018, PP. 3598–3600 (scopus).
• P.Nagarajan , T.Kavitha and P Venkat Ramana, “Design and Evaluation of Power Efficient Shift Register Featuring Low Power Automatic Manufacturing Systems” Solid State Technology, ISSN: 0038-111X, Vol.63, Issue 5 ,2020. (Scopus).
• P Nagarajan, Kavitha Thandapani, N Ashokkumar, C Kanmani Pappa, “Design and Analysis of Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization” published in IEEEXplore, DOI:10.1109/ICOSEC58147.2023.10275837 , Publisher: IEEE, 20-22 September 2023, pp.01-05 (Scopus).
• P Nagarajan, N Ashok Kumar, Joshuva Arockia Dhanraj, T Senthil Kumar, “ Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture ” published in IEEEXplore, DOI: 10.1109/ICEARS53579.2022.9752249, Publisher: IEEE, 13 April 2022, pp.410-414 (Scopus).
• N Ashok Kumar, P Nagarajan, Joshuva Arockia Dhanraj, T Senthil Kumar, “ Analysis of Millimeter-Wave based on Multichannel Wireless Networks-on-Chip ” published in IEEEXplore, DOI: 10.1109/ICEARS53579.2022.9752077 , Publisher: IEEE, 13 April 2022, pp.405-409 (Scopus)
• L Mohana Sundari, T Senthil Kumar, P Nagarajan, UNVP Rajendranath, Ngangbam Phalguni Singh,” ICLM: Empirical Evaluation of Rheumatoid Arthritis Disorder using Image Classification and Linear Mapping Principles ” published in IEEEXplore, DOI:10.1109/ICEARS53579.2022.9752400, Publisher: IEEE, 13 April 2022, pp. 1120-1126 (Scopus)
• P. Nagarajan, P Venkatramana,  Shaik Javid Basha , “Design of Three-valued Logic Half-Subtractor using GNRFET” published in IEEExplore, DOI: 10.1109/RAEEUCCI57140.2023.10134349, Publisher: IEEE, 30 May 2023, (Scopus).
• P. Nagarajan, P Venkatramana,  Shaik Javid Basha , “Design of SB-GNRFET and D-GNRFET using QuantumATK” published in IEEExplore, DOI:10.1109/ICNWC57852.2023.10127562 , Publisher: IEEE, 25 May 2023, (Scopus).
• P. Nagarajan, Kavitha Thandapani, C.Kanmani pappa, and N Ashok kumar, “MEMS Sensor Based V2V Communication Using Li-Fi Technology” published in IEEExplore, DOI:10.1109/ICACCS57279.2023.10112879, Publisher: IEEE, 5 May 2023, (Scopus).
• P. Nagarajan, C.Kanmani pappa , N Ashok kumar and Kavitha Thandapani, “Bluetooth based Garage Door Opening System” published in IEEExplore, DOI:10.1109/ICSSIT55814.2023.10061046 , Publisher: IEEE, 14 March 2023, (Scopus).
• P. Nagarajan, R.Rama Devi, T.Kowsalya and D.Sathish Kumar “Health Care Assistive System in Hospital for Doctor to View the Patient’s Parameter in a Cloud Database using Light Fidelity” published in IEEExplore, DOI: 10.1109/I-SMAC55078.2022.9987390 , Publisher: IEEE, 22 December 2022, (Scopus).
• P Nagarajan, R Ramadevi, D Lakshmi, T Kowsalya, S Jensie Anita “Foetal ultrasonographic Sparse representation evaluation of spectral trust maps” published in AIP Conference Proceedings , https://doi.org/10.1063/5.0110574 , Publisher: AIP, 30 January 2023, (Scopus).
• N Ashokkumar , P Nagarajan, and P Venkat Ramana , “ NoC : A Frame Work for 2-dimensional and 3-dimentional architectures”, journal of advanced research in dynamical and control systems, JARDCS , ISSN :1943-023X, Vol.9, Issue 14,April 2017, PP.2686-2694 ( Elsevier Scopus).
• P.Nagarajan , T.Kavitha and S.Shiyamala ,“Efficient timing element design featuring low power vlsi application” International Journal of Engineering and Technology (IJET), ISSN (Online) : 0975-4024, Vol 8 No 4, Aug-Sep 2016, PP. 1696-1705 (scopus).
• P.Nagarajan , T.Kavitha and A.Arulmary, “Radio over fiber on gigabit passive optical network using QPSK modulation scheme” Journal of Optical Communications (JOC), ISSN: 2191-6322, Published online: 30 Nov 2020. (Elsevier Scopus).
• P.Nagarajan , T.Kavitha and S. Shiyamala, “FPGA implementation of arbiters algorithm for network-on-chip” ARPN Journal of Engineering and Applied Sciences, ISSN 1819-6608, Published online: VOL. 11, NO. 19, OCTOBER 2016. (Elsevier Scopus).
• P.Nagarajan , S.GowdhamKumar, Dr. R.M.Sekar, and Dr.S.Sivaranjani, “ Digital Design Systems Controlling Using FPGA Realization” Annals of R.S.C.B, ISSN1583-6258, , Vol.25, Issue 5, 2021, PP. 570-582 . (Elsevier Scopus).
• P.Nagarajan , S.GowdhamKumar, Dr. R.M.Sekar, and Dr.S.Sivaranjani, “A study on Strategies of Trading the News Using Massive Data Mining” , published in IEEEXplore, DOI:  10.1109/CCICT53244.2021.00029 , Publisher: IEEE Xplore, 24 August 2021 (Scopus)
• Gabariyala Sabadini C, P. Maniraj Kumar & P.Nagarajan “Design And Analysis Of Double Edge Triggered Clocked Latch For Low Power VLSI Applications” published in IEEE Xplore , DOI: 10.1109/ISCO.2016.7727012 , Publisher: IEEE, 03 November 2016, (Scopus).
• P.Nagarajan, R.Saravanan and P.Thirumurugan 2014 “Design of register element for low power clocking system”, Information-An International Interdisciplinary Journal, ISSN 1343-4500(print), ISSN 1344-8994(electronic) Vol.17, no.6(B), pp.2903-2913, July 2014 (Annexure I – Impact Factor: 0.36) (Scopus)
• Vithyalakshmi.N1, Nagarajan.P, Ashok Kumar.N, Vinoth.G.S, “Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review” International Journal of Engineering & Technogy, ISSN: 2227-524XVolume 7(3.1), 2018,34-38, (Scopus)
• Arthi C K and Nagarajan P 2015 “Design Of Sequential Elements For Low Power VLSI Applications”, International Journal of Applied Engineering Research ISSN 0973-4562 Vol. 10 No.5 (2015) pp. 4872-4876,(Annexure II) (Scopus)
• T. Kavitha, S. Shiyamala & P. Nagarajan, ‘FPGA implementation of arbiters algorithm for network-on-chip’ ARPN Journal of Engineering and Applied Sciences, ISSN 1819-6608, VOL. 11, NO. 19, October 2016, PP.11451-11456 (Scopus).
• Dr. S. Shiyamala, Dr. T. Kavitha & Dr. P. Nagarajan, “Real time motion detection and tracking system by Kalman filter”, Journal of Theoretical and Applied Information Technology, ISSN: 1992-8645, Vol.95, No.16, 31st August 2017, PP .3851-3860 (Scopus).
• P. Jeya Priyanka, Dr. K. Batri and Dr.P.Nagarajan, “Design and Analysis of Explicit Pulsed Register Element for Low Power VLSI Circuits”, Advances in Natural and Applied Sciences (ANAS), ISSN: 1995-0772, Special 9(17): 2015, PP.136-144.(Scopus)
• Palagiri Avaneesh , Dr. P.Nagarajan, “Design and Functional Verification of DDR SDRAM Controller to Access Multiple Banks”, Journal of Emerging Technologies and Innovative Research (JETIR), ISSN: 2349-5162, Volume 5, Issue 5 May 2018. PP.52-58 (UGC Listed)
• Ellasamudram Durga , Dr. P.Nagarajan, “A Novel Design of Low Power and Area Efficient Line Decoder”, Journal of Emerging Technologies and Innovative Research (JETIR), ISSN: 2349-5162, Volume 6, Issue 6 June 2019. PP.593-600 (UGC Listed)
• P.Nagarajan and R.Saravanan 2013 “Design and Analysis of Register Element for Low Power Clocking System” ,International Journal of Computer Science and Mobile Computing, ISSN 2320–088X, Vol. 2, Issue 4,pp.38-45. (UGC Listed)
• P.Nagarajan and P.Jenifer Martina 2013 “Hand Gesture Recognition Based Real-time Command System” ,International Journal of Computer Science and Mobile Computing, ISSN 2320–088X, Vol. 2, Issue 4,pp.295-299. (UGC Listed)
• M. Guru Santhana Bharathi and P.Nagarajan 2014 “Design of Storage Element for Low Power VLSI System”, IJISET – International Journal of Innovative Science, Engineering & Technology, ISSN 2348 – 7968, Vol. 1 Issue 3. (UGC Listed)
• P.Nagarajan and K.Nithya 2014 “Power Efficient Design of BILBO using Various Sequential Elements for Low power VLSI Applications (Basic5T-transistor and 5T- with MTCMOS)”, International Journal of Engineering Sciences & Research Technology. ISSN: 2277-9655 pp.835-841 ( Impact Factor : 1.852)
• S.Meena and P.Nagarajan 2014 “Power Efficient Design of Bilbo by Using Various Clocked Latches”, International Journal of Innovative Research in Science, Engineering and Technology, ISSN: 2319 – 8753, Volume 3, Special Issue 3, pp.1427-1434.
• Gabariyala Sabadini C, Dr. P. Maniraj Kumar & Dr. P.Nagarajan “Design And Analysis Of Implicit Pulsed Double Edge Triggered Clocked Latch For Low Power Applications”, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), ISSN: 2278-909X Volume 4, Issue 11, November 2015. pp.2672–2678.
• P.Jothimani and Dr.P.Nagarajan, “Smart Vehicle System Design For Road Condition And Detection Of Potholes And Humps On Road To Aid Drivers”, International Journal of Advanced and Innovative Research (2278-7844) / # 105 / Volume 4 Issue 11, 2015 ,pp.105-108.

• P Nagarajan, Kavitha Thandapani, N Ashokkumar, C Kanmani Pappa, “Design and Analysis of
  Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization”
  published in IEEEXplore, DOI: 10.1109/ICOSEC58147.2023.10275837 , Publisher: IEEE,
  20-22 September 2023, pp.01-05. 4th International Conference on Smart Electronics and
  Communication (ICOSEC).
• P Nagarajan, Kavitha Thandapani, N Ashokkumar, C Kanmani Pappa, “Design and Analysis of
  Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization”
  published in IEEEXplore, DOI: 10.1109/ICOSEC58147.2023.10275837 , Publisher: IEEE,
  20-22 September 2023, pp.01-05. 4th International Conference on Smart Electronics and
  Communication (ICOSEC).
• P Nagarajan, N Ashok Kumar, Joshuva Arockia Dhanraj, “ Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture ” published in IEEE Xplore , DOI: 10.1109/ISCO.2016.7727012 , Publisher: IEEE, 03 March 2022, International Conference on Electronics and Renewable Systems (ICEARS).
• N Ashok Kumar, P Nagarajan, Joshuva Arockia Dhanraj, T Senthil Kumar, “ Analysis of Millimeter-Wave based on Multichannel Wireless Networks-on-Chip ” published in IEEEXplore, DOI: 10.1109/ICEARS53579.2022.9752077 , Publisher: IEEE, 03 March 2022,International Conference on Electronics and Renewable Systems (ICEARS).
• P.Nagarajan, “Low power VLSI design approaches for CMOS and CNTFET based circuits design”, International conference on Recent trends in Information, Communication and Pervasive Technologies (ICRTICPT – 2022) May 2022, Tamilnadu, India.
• P.Nagarajan, “Design and Evaluation of single edge triggering flip flop using split path technique for low power VLSI architectures”, International conference on Recent trends in Information, Communication and Pervasive Technologies (ICRTICPT – 2022) May 2022, Tamilnadu, India.
• P. Nagarajan, P Venkatramana,  Shaik Javid Basha , “Design of Three-valued Logic Half-Subtractor using GNRFET” International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI) , 30 May 2023.
• P. Nagarajan, P Venkatramana,  Shaik Javid Basha , “Design of SB-GNRFET and D-GNRFET using QuantumATK” International Conference on Networking and Communications (ICNWC), 25 May 2023.
• P. Nagarajan, Kavitha Thandapani, C.Kanmani pappa, and N Ashok kumar, “MEMS Sensor Based V2V Communication Using Li-Fi Technology” International Conference on Advanced Computing and Communication Systems (ICACCS), 5 May 2023.
• P. Nagarajan, C.Kanmani pappa , N Ashok kumar and Kavitha Thandapani, “Bluetooth based Garage Door Opening System” 5th International Conference on Smart Systems and Inventive Technology (ICSSIT) , 14 March 2023.
• P. Nagarajan, R.Rama Devi, T.Kowsalya and D.Sathish Kumar “Health Care Assistive System in Hospital for Doctor to View the Patient’s Parameter in a Cloud Database using Light Fidelity”, Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC) , December 2022.
• P Nagarajan, R Ramadevi, D Lakshmi, T Kowsalya, S Jensie Anita “Foetal ultrasonographic Sparse representation evaluation of spectral trust maps” RECENT ADVANCEMENT IN MECHANICAL ENGINEERING AND INDUSTRIAL MANAGEMENT, June 2021.
• P.Nagarajan, “Investigating Wireless Optical Communication Systems for Inter Satellite Communication using QPSK Modulation Technique”, International conference on Data Intelligence and Cognitive Informatics (ICDICI – 2019) July 2021, Tamilnadu, India.
• P.Nagarajan, R.Saravanan , “Power efficient design of storage element for low power VLSI system”, International conference on recent innovations in engineering (ICRIE 2014), Tamilnadu, India.
• P.Nagarajan, “Design and functional verification of DDRSDRAM controller to access multiple banks”, International conference on electrical, electronics and communication engineering (ICEECE-2018), Hyderabad, India.
• N.Ashokkumar, P.Nagarajan, “3D Router Communication based Mixed on Chip topology”, International conference on innovation in science and engineering research (ICISER’18) March 2018, Chennai, India.
• N.Ashokkumar, P.Nagarajan, “3D Wired and Wireless Network on Chip NoC”, International conference on Inventive Communication and computational Technologies (ICICCT’19) April 2019, Namakkal, India.
• N.Ashokkumar, P.Nagarajan, “Design challenges for 3 Dimensional Network-on-Chip (NoC)”, International conference on sustainable Communication networks and Application (ICSCN’19) July 2019, Erode, India.
• P.Nagarajan, “Review on Flip flops for Low power and High performance VLSI clocking system”, International conference on applications of mems, nano and smart materials (ICMNSM – 2019) December 2019, Tiruapati, India.
• P.Nagarajan, “A Design and evaluation of parallel to serial data converter featuring low power digital CMOS VLSI Systems”, International conference on applications of mems, nano and smart materials (ICMNSM-2019) December 2019, Tiruapati, India.
• Gabariyala Sabadini C, Dr. P. Maniraj Kumar & Dr. P.Nagarajan “Design And Analysis Of Double Edge Triggered Clocked Latch For Low Power VLSI Applications” 10 th International Conference on Intelligent Systems and Control (ISCO) January 2016, DOI:10.1109/ISCO.2016.7727012 (published in IEEE Xplore: 03 November 2016)
• S.Meena, P.Nagarajan 2014 “Power Efficient Design of Bilbo By Using Various Clocked Latches” International Conference on Innovations in Engineering and Technology (ICIET’14), Madurai, India.
• M. Guru Santhana Bharathi, P.Nagarajan “ Power efficient design of Storage Element for Low Power VLSI System” International conference on recent innovations in engineering (ICRIE 2014), Palani, India.
• P.Nagarajan, P.Jenifer Martina “Hand Gesture Recognition Based Real- time Command System”, International conference on innovation in intelligent instrumentation 2013, optimization and signal processing, coimbatore, India.
• P.Nagarajan “Performance Analysis of Broadband OFCDMA system” National conference on ESIC’09, Dindigul, India.

Patents Published :

• Title of the invention: “IOT-DRIVEN REAL-TIME STRUCTURAL HEALTH MONITORING AND DAMAGE IDENTIFICATION USING AI”, Application No. 202341026223 A, Publication Date: 05/05/2023.
• Title of the invention: “MEDICAL WASTE TREATMENT DEVICE”, Application No. 383823-001, Publication Date: 13/04/2023.
• Title of the invention: “MACHINE LEARNING BASED TECHNIQUE INTEGRATED WITH SIX SIGMA METHODOLOGIES FOR PREDICTING THE STRESS OF EMPLOYEES IN AN ORGANIZATIOIN”, Application No. 202241057567, Publication Date: 07/10/2022.
• Title of the invention: “HYBRID STORAGE ARCHITECTURE FOR IoT”, Application No. 202241033343, Publication Date: 17/06/2022.
• Title of the invention: “DESIGN OF RISING EDGE TRIGGERING FLIP FLOP USING PSEUDO-NMOS TECHNIQUE FOR LOW POWER CLOCKING SYSTEM”. Application No. 201941048075, Publication Date: 28/05/2021.
• Title of the invention: A SIMPLE AND EFFECTIVE DEVICE FOR DETECTION AND DIAGNOSING THE EARLIAR DIABETES THYROID UBNORMAL, Application No. 201941013976 A, Publication Date: 17/05/2019.
• Title of the invention: DESIGN OF DOUBLE EDGE TRIGGERED MASTER SLAVE FLIP-FLOP USING A NOVEL PARALLEL SLEEPY STACK TECHNIQUE, Application No. 201741032973 A, Publication Date: 22/03/2019.
• Title of the invention: DESIGN OF POWER GATED DOUBLE EDGE TERIGGERED FLIP
  FLOP USING SLEEP TRANSISTOR TECHNIQUE (PG-STDETFF), Application No.201741000167 A, Publication Date: 02/06/2017.
• Title of the invention: DESIGN OF IMPLICIT PULSED -DOUBLE EDGE TRIGGERED ELIP
  FLOP (IP-DETFF) FOR LOW POWER CLOCKING SYSTEM. Application No.201641042620
  Publication Date: 02/06/2017

Patents Granted :

• Title of the invention: DESIGN OF POWER GATED DOUBLE EDGE TERIGGERED FLIP
  FLOP USING SLEEP TRANSISTOR TECHNIQUE (PG-STDETFF), ApplicationNo.201741000167, Publication Date: 02/06/2017. Field of Invention: Electronics. Patent No: 534840, Date of Grant: 25/04/2024.

Patents Registered :

• Title of the invention: “Three Dimensional (3D 4X4X3) Social Based Network on Chip Architecture (NoC)”. Application No. 201841000052. CBR No. 20.

• Published a Book titled “VLSI Design “in SCHOLAR’S PRESS publication, Print ISBN:978-620-5-52397-1, https://images.our-assets.com/fullcover/2000x/9786205523971.jpg, July 2023.
• Published a book titled “Advanced Digital System Design “in SCHOLAR’S PRESS publication, ISBN: 978-613-8-91046-6, December 2022.
• Published a book titled “Advanced Embedded System Design “in LAP LAMBERT Academic Publishing, ISBN: 978-3-030-03145-9, ISBN-13:978-6200117625, ISBN-10: ‎6200117624 July 5, 2021.
• P. Nagarajan, Kavitha T , Arul Mary, “Distributed optical fiber sensing system for leakage reduction in underground energy storage pipeline using Machine –learning techniques “ materials for sustainable energy storage at Nano Scale– CRC PRESS, Taylor & Francis , June 2023.
• Published a lecture notes on “ Investigating Wireless Optical Communication Systems for İnter Satellite Communication Using QPSK Modulation Technique“ in the book titled “Algorithms for Intelligent Systems” in Springer publication , ISBN: 978-981-16-6460-1 DOI: 10.1007/978-981-16-6460-1_66, pp 849-856 ,01st February 2022 .
• Published a book chapter named “3D (Dimensional) – wired and wireless network-on-chip (NoC) “in the book titled “NETWORKS AND SYSTEMS” “in Springer publication, Online ISBN: 978-981-15-0146-3, Print ISBN: 978-981-15-0145-6, DOI: https://doi.org/10.1007/978-981-15- 0146-3_12, pp113-119, 30th January 2020.
• Published a book chapter named “Design challenges for 3 Dimensional Network-on-Chip (NoC) “in the book titled “Sustainable communication networks and application “in Springer publication, Online ISBN: 978-3- 030-34515-0, PrintISBN:978-3-030-34514-3, DOI: https://doi.org/10.1007/978-3-030-34515-0_82, November 2019. pp773- 782
• Published a lecture notes on “ Quad-Rail Sense-Amplifier based NoC Router Design “ in the book titled “Data Engineering and Communication Technologies“ in Springer publication , ISBN: 978-953-51-3864-8, Print ISBN: 978-953-51-3863-1, DOI: 1007/978-3-030-03146-6, pp.1449- 1454 January 2019.
• Published a book chapter named “Low Power Design Methodology “ in the book titled “Very-Large-Scale Integration“ in INTECH OPEN publication , ISBN: 978-3-030-03145-9, Print ISBN: : 978-3-030-03146- 6, DOI: 10.5772/65525, February 2018

• Participated 4 day residential Workshop on “Design Thinking” Conducted by intellect School of Design Thinking Collaborated with SRMIST on June 2023. Venue : 8012 FinTech Design Center, Siruseri, Chennai.
• Participated one day Awareness/ Training Program on “Intellectual Property Rights” Under National Intellectual Property Awareness Mission – NiPAM Conducted by intellectual Property Office, India on 26 th October 2023.
• Conducted two day national workshop for researchers on “VLSI architectures for biomedical image processing Applications” fully sponsored by CSIR.
• Organized Six day Faculty Development Programme on “High Performance VLSI Architectures for Multidisciplinary Applications”
• Organized Six day AICTE Sponsored Short Term Training Programme on “ Recent Trends Research Challenges on Nano CMOS VLSI Circuits by industry Standard EDA Tools”
• Conducted two day seminar on “Transmission lines and waveguides with KETAB STUDIO V4.0.0 Lite”.
• Conducted two day workshop on “Recent Research Tools for VLSI Design”. (Tanner, Microwind. Cadence).

• Delivered guest lecture as resource person on “MOTIVATION OF STUDENTS TOWARDS CONVERSION OF PROJECT INTO PATENT” in the webinar conducted by IPR Cell at NPR College of engineering and technology, Dindigul, May 2023.
• Delivered guest lecture as resource person on “LOW POWER VLSI DESIGN METHODOLOGIES FOR CMOS and CNTFET BASED CIRCUITS AND SYSTEMS” for summer vacation 2020 at SSM Institute of engineering and technology, Dindigul
• Delivered guest lecture as resource person on “CARBON NANOTUBE FIELD EFFECT TRANSISTORS – FABRICATION AND APPLICATIONS” for 6 days FDTP at Sree Vidyanikethan Engineering College, Tirupati, and Andhra Pradesh.
• Delivered guest lecture as resource person in Anna University approved faculty development training programme (FDTP) on “EMBEDDED & REAL TIME SYSTEMS” titled “ POWER EFFICIENT METHODOLOGIES TO DESIGN LOW POWER VLSI CIRCUITS FOR EMBEDDED REAL TIME SYSTEMS” for Summer vacation 2022 at AMRITA Vishwa Vidyapeetham University. Bangalore.
• Delivered guest lecture as resource person in National level webinar on “Metal Oxide Semiconductor and Carbon Nano Tube Field Effect Transistors” through zoom platform on
  June 2020 at TDMNS College, Tamilnadu.
• Delivered guest lecture as resource person in Anna University approved faculty development training programme (FDTP) on “VLSI DESIGN” for winter vacation 2016 at SSM Institute of engineering and technology, Dindigul.
• Delivered guest lecture as resource person in Anna University approved faculty development training programme (FDTP) on “DIGITAL SIGNAL PROCESSING” for summer vacation 2017 at SSM Institute of engineering and technology, Dindigul.
• Delivered guest lecture as resource person in Anna University approved faculty development training programme (FDTP) on “ELECTROMAGNETIC FIELDS” for winter vacation 2017 at Adhi College of engineering and technology, Kanchipuram.

• Completed 8 Week online Certification course titled “Road Map for Patent Creation” Conducted by NPTEL – AICTE , Swayam with Consolidated score of 81% , Secured Elite in the duration of January-March 2023.
• Completed 4 Week online Certification course titled “Design Thinking – A Primer” Conducted
  by NPTEL – AICTE, Swayam with Consolidated score of 75% , Secured Elite in the duration of
  July-August 2023.

• Working as Associate Professor in SRMIST, Vadapalani Campus from 30/01/23
• Worked as Professor in Rajalakshmi Institute of Technology, Chennai from 05/10/20 to 27/01/23
• Worked as Associate Professor in Sree Vidyanikethan Engineering college. Tirupati from 17/07/17 to 04/10/20
• Worked as Associate Professor in VEL Tech University- Chennai from 19/02/16 to 14/07/17
• Worked as Lecturer, Assistant Professor in PSNA College of Engineering and Technology – Dindigul from 30/05/09 to 18/02/16
• Worked as Teaching Assistant in RVS College of Engineering and Technology,Dindigul from 05/10/07 to 29/05/09

NIL